Tag Archives FEC

One of the great challenges facing data communications is matching the silicon bandwidth with the face plate density. Today, switch silicon can process over 12 Tb/s. But getting this off the front panel at a reasonable density is a challenge. One direction is to move to faster Ethernet speeds. A great example of this is […]

With the move to pluggable coherent optical modules for the first time since 10G, we see client and line side considerations coming together. The most obvious example of this is optical signal to noise (OSNR) and related measurements. For any modules with the potential for use in an amplified system, OSNR becomes the fundamental figure […]

With the advent of 400G Ethernet, it has become critically important to fully understand and validate Forward Error Correction (FEC) logic and the related software and firmware. 400G Ethernet uses PAM-4 signalling optically and electrically. Because of the susceptibility to the impact of noise, distortion, and other disturbances, most links will run with a raw error […]

Optical interconnectivity at 400 Gbps has introduced many new design challenges. These include the step from NRZ to PAM-4 coding with the presence of a background error rate, the new QSFP-DD form factor for transponders with thermal and integration challenges and aggressive cost expectations early in the lifecycle.  One of the most difficult challenges is […]

In this Olympic year, the motto Citius, Altius, Fortius (Latin for Faster, Higher, Stronger) seems very relevant to where we are with Ethernet networking. We need faster bandwidth, higher levels of service and stronger performance to push around all those videos of cats—as well as the more serious (and less cute) business traffic. Approximately every […]

VIAVI Perspectives