VIAVI 400G FEC Validation Test Suite Addresses the Most Challenging FEC Design Areas

Optical interconnectivity at 400 Gbps has introduced many new design challenges. These include the step from NRZ to PAM-4 coding with the presence of a background error rate, the new QSFP-DD form factor for transponders with thermal and integration challenges and aggressive cost expectations early in the lifecycle.  One of the most difficult challenges is around the FEC (Forward Error Correction) logic. VIAVI is a pioneer in 100G and 400G FEC stress testing, and the ONT test platform provides designers and developers a means to address the challenges with FEC logic.

FEC allows the PAM-4 links used on both the electrical and optical channels at 400 Gbps to run error free. The FEC used at 400GE is a Reed Solomon, RS KP4FEC and it has been carefully designed to provide p

rotection against the wide spectrum of errors that can occur on a high-speed links while balancing the needs of complexity (ASIC/FPGA area and power) and latency performance.

The testing and validation of this FEC logic functionality is a significant challenge, but it is critical to ensure successful 400G deployment and inter-operability. The number of potential dynamic error combinations is huge, and to get full confidence in the FEC functionality, it is important to stress the circuitry in various aspects.

The RS KP4 FEC as defined for 400GE uses a 544 symbol codeword with 10 bit symbols and has the ability to detect and correct up to 15 errored symbols in a given codeword. The input codeword of 514 symbols is expanded by the 30 parity symbols which provide protection against errors.

VIAVI developed the concept of FEC stress testing with 100G and 400G which has allowed the ecosystem to develop robust logical implements and have confidence in the performance of the logic and ensure inter-operability across all vendors.

FEC logic stress testing applies a deterministic set of errored codewords that can be targeted to specific row/column patterns to maximize the stress. The errored symbol count can be ramped and scattered across the codeword and the VIAVI ONT test platform provides an optimal section of errored symbol counts that allows confidence testing in a reasonable timescale.

This has now been taken a step further with the addition of the VIAVI power integrity FEC stress application.

One challenge with FEC validation has been dynamic performance. The FEC logic is typically implemented as arrays of XOR gates. When receiving errored symbols, additional rows of XOR gates will ‘flip’ – this causes a dynamic current draw. These spikes occur at the codeword rate and there is the chance that these current spikes will cause voltage drops through power supply integrity issues. The current (and corresponding) voltage spikes can cause circuit malfunction which can be almost impossible to trace. The VIAVI power integrity FEC stress application carefully targets power draw transients into the FEC logic and determines if any power integrity failure modes can be excited.

Such an application is invaluable if the ‘whole’ FEC functionality is to be validated – power supply integrity issues could be caused by both internal power layout inside the IC as well as external point of load and decoupling elements. Many FEC implementations are also realized in FPGA which are particularly layout sensitive. Power integrity FEC stress testing will help validate floor planning and layout choices.

Only the combination of the above described FEC logic and FEC power integrity stress tests will give developers and designers the necessary confidence that the complex FEC circuitry works flawlessly under all operating conditions.

To see our solutions first-hand, we invite you to visit us at OFC 2019 in San Diego, California, March 3-7.  VIAVI is in booth 2814.  We also invite you to explore our 400G web page and learn more about our industry-leading 400G test solutions.